High Throughput and Cost Efficient VLSI Architecture of Integer Motion Estimation for H.264/AVC

Variable block size motion estimation (VBS-ME) is one of the contributors to H.264/AVC’s excellent coding efficiency. Due to its high computational complexity, however, VBS-ME needs acceleration for real-time high-resolution applications. This paper proposes a high throughput and cost efficient VLSI architecture for integer full-search VBS-ME in H.264/AVC. A new scan order is introduced to re-use the reference data, 16 4x4 SAD generators in parallel can produce 16 4x4 SADs at the same time, an adder tree unit can produce larger block’s SAD by using these small 4x4SADs. Integer-pixel ME module produces two groups of 41 integer motion vectors (IMVs) synchronously by checking two candidate points in parallel. After logic synthesis using SMIC 0.13 μm standard cell library, under a clock frequency of 300MHz, the integer ME architecture allows the processing of 1280x720(720HD) at 38fps with full search block matching algorithm(FS-BMA) in a search range [-32, +32].